QPSK调制解调通信系统设计Verilog代码Quartus仿真

名称：QPSK调制解调通信系统设计Verilog代码Quartus仿真

软件：Quartus

语言：Verilog

代码功能：

QPSK调制解调通信系统

FPGA代码Verilog/VHDL代码资源下载：www.hdlcode.com

演示视频：

设计文档：

1.工程文件

2.程序文件

3.程序编译

4.RTL图

5.Testbench

部分代码展示:

`timescale?1ns?/?1ps
//////////////////////////////////////////////////////////////////////////////////
//?Company:?
//?Engineer:?
//?
//?Create?Date:?2023/05/03?06:02:38
//?Design?Name:?
//?Module?Name:?filter
//?Project?Name:?
//?Target?Devices:?
//?Tool?Versions:?
//?Description:?
//?
//?Dependencies:?
//?
//?Revision:
//?Revision?0.01?-?File?Created
//?Additional?Comments:
//?
//////////////////////////////////////////////////////////////////////////////////
`timescale?1ns?/?1ps
//////////////////////////////////////////////////////////////////////////////////
//?Company:?
//?Engineer:?
//?
//?Create?Date:?2023/04/23?22:16:21
//?Design?Name:?
//?Module?Name:?fiter
//?Project?Name:?
//?Target?Devices:?
//?Tool?Versions:?
//?Description:?
//?
//?Dependencies:?
//?
//?Revision:
//?Revision?0.01?-?File?Created
//?Additional?Comments:
//?
//////////////////////////////////////////////////////////////////////////////////
module?fiter(
input?i_clk,
input?i_rst,
input?signed[1:0]i_din,
output?signed[15:0]o_dout
);
//滤波器系数
parameter?b0?=??174;
parameter?b1?=??63;?
parameter?b2?=??-307;??
parameter?b3?=??-642;??
parameter?b4?=??-435;???
parameter?b5?=??642;???
parameter?b6?=??2370;
parameter?b7?=??3992;
parameter?b8?=??4656;
parameter?b9?=??3992;
parameter?b10=??2370;
parameter?b11=??642;??????
parameter?b12=?-435;??????
parameter?b13=?-642;???????
parameter?b14=?-307;?????
parameter?b15=?63;??????
parameter?b16=?174;?
?????????
?
?????????
reg?signed[1:0]x0;
reg?signed[1:0]x1;
reg?signed[1:0]x2;
reg?signed[1:0]x3;
reg?signed[1:0]x4;
reg?signed[1:0]x5;
reg?signed[1:0]x6;
reg?signed[1:0]x7;
reg?signed[1:0]x8;
reg?signed[1:0]x9;
reg?signed[1:0]x10;
reg?signed[1:0]x11;
reg?signed[1:0]x12;
reg?signed[1:0]x13;
reg?signed[1:0]x14;
reg?signed[1:0]x15;
reg?signed[1:0]x16;
//xn延迟
always?@(posedge?i_clk?or?posedge?i_rst)
begin
?????if(i_rst)
??begin
??x0?<=?2'd0;
??x1?<=?2'd0;
??????x2?<=?2'd0;
??????x3?<=?2'd0;
??????x4?<=?2'd0;
??????x5?<=?2'd0;
??????x6?<=?2'd0;
??x7?<=?2'd0;
??x8?<=?2'd0;
??????x9?<=?2'd0;
??????x10?<=?2'd0;
??????x11?<=?2'd0;
??????x12?<=?2'd0;
??????x13?<=?2'd0;?
??????x14?<=?2'd0;
??????x15?<=?2'd0;
??????x16?<=?2'd0;?
??end
else?begin
??x0?<=?i_din;
??x1?<=?x0;
??????x2?<=?x1;
??????x3?<=?x2;
??????x4?<=?x3;
??????x5?<=?x4;
??????x6?<=?x5;?
??x7?<=?x6;
??????x8?<=?x7;
??????x9?<=?x8;
??????x10?<=?x9;
??????x11?<=?x10;
??????x12?<=?x11;?
??x13?<=?x12;
??????x14?<=?x13;
??????x15?<=?x14;

点击链接获取代码文件：http://www.hdlcode.com/index.php?m=home&c=View&a=index&aid=1359