基于FPGA的16bit乘法器组成64bit算术乘法器Verilog代码Quartus仿真

名称：基于FPGA的16bit乘法器组成64bit算术乘法器Verilog代码Quartus仿真

软件：Quartus

语言：Verilog

代码功能：

Verilog HDL设计64bits算术乘法器

基本功能：

1.用 Veriloghdl设计实现64bit二进制整数乘法器,底层乘法器使用16*168*88*328*16小位宽乘法器来实现底层乘法器可以使用FPGA内部P实现;

2.基于 mode sim仿真软件对电路进行功能验证;

3.基于 Quartus平台对代码进行综合及综合后仿真,芯片型号不限;

4.电路综合后的工作频率不低于50MHz。

提交 Veriloghdl设计代码,代码具有可综合性;

分别给出综合前后的仿真结果,并对比分析

给出综合后电路的硬件资源及性能(如工作速度)等相关数据,简要分析资源和性能之间的关联性

FPGA代码Verilog/VHDL代码资源下载：www.hdlcode.com

演示视频：

设计文档：

1. 工程文件

2. 程序文件

3. 程序编译

4. RTL图

5. Testbench

6. 仿真图

可以看到，乘积正确

综合后仿真

资源

仿真图

FMAX最大时钟

部分代码展示:

module?Multiplier64(
input?clk,
input?[63:0]?multiplier_x,//乘数x
input?[63:0]?multiplier_y,//乘数y
output?[127:0]?product//输出结果
);
//信号定义
wire?[15:0]?multiplier_x_1;
wire?[15:0]?multiplier_x_2;
wire?[15:0]?multiplier_x_3;
wire?[15:0]?multiplier_x_4;
wire?[15:0]?multiplier_y_1;
wire?[15:0]?multiplier_y_2;
wire?[15:0]?multiplier_y_3;
wire?[15:0]?multiplier_y_4;
wire?[31:0]?product_x1y1;
wire?[31:0]?product_x1y2;
wire?[31:0]?product_x1y3;
wire?[31:0]?product_x1y4;
wire?[31:0]?product_x2y1;
wire?[31:0]?product_x2y2;
wire?[31:0]?product_x2y3;
wire?[31:0]?product_x2y4;
wire?[31:0]?product_x3y1;
wire?[31:0]?product_x3y2;
wire?[31:0]?product_x3y3;
wire?[31:0]?product_x3y4;
wire?[31:0]?product_x4y1;
wire?[31:0]?product_x4y2;
wire?[31:0]?product_x4y3;
wire?[31:0]?product_x4y4;
reg?[127:0]?product_x1y1_full;
reg?[127:0]?product_x1y2_full;
reg?[127:0]?product_x1y3_full;
reg?[127:0]?product_x1y4_full;
reg?[127:0]?product_x2y1_full;
reg?[127:0]?product_x2y2_full;
reg?[127:0]?product_x2y3_full;
reg?[127:0]?product_x2y4_full;
reg?[127:0]?product_x3y1_full;
reg?[127:0]?product_x3y2_full;
reg?[127:0]?product_x3y3_full;
reg?[127:0]?product_x3y4_full;
reg?[127:0]?product_x4y1_full;
reg?[127:0]?product_x4y2_full;
reg?[127:0]?product_x4y3_full;
reg?[127:0]?product_x4y4_full;
//64bit拆分
decompose?i0_decompose(
.?clk(clk),
.?multiplier(multiplier_x),//64bit拆输入
.?multiplier_1(multiplier_x_1),//拆分为4个16bit
.?multiplier_2(multiplier_x_2),//拆分为4个16bit
.?multiplier_3(multiplier_x_3),//拆分为4个16bit
.?multiplier_4(multiplier_x_4)//拆分为4个16bit
);
//64bit拆分
decompose?i1_decompose(
.?clk(clk),
.?multiplier(multiplier_y),//拆分为4个16bit
.?multiplier_1(multiplier_y_1),//拆分为4个16bit
.?multiplier_2(multiplier_y_2),//拆分为4个16bit
.?multiplier_3(multiplier_y_3),//拆分为4个16bit
.?multiplier_4(multiplier_y_4)//拆分为4个16bit
);
//调用16个16*16的乘法器IP
Multiplier_16x16??Multiplier_16x16_11(multiplier_x_1?,multiplier_y_1?,product_x1y1);
Multiplier_16x16??Multiplier_16x16_12(multiplier_x_1?,multiplier_y_2?,product_x1y2);
Multiplier_16x16??Multiplier_16x16_13(multiplier_x_1?,multiplier_y_3?,product_x1y3);
Multiplier_16x16??Multiplier_16x16_14(multiplier_x_1?,multiplier_y_4?,product_x1y4);
Multiplier_16x16??Multiplier_16x16_21(multiplier_x_2?,multiplier_y_1?,product_x2y1);
Multiplier_16x16??Multiplier_16x16_22(multiplier_x_2?,multiplier_y_2?,product_x2y2);
Multiplier_16x16??Multiplier_16x16_23(multiplier_x_2?,multiplier_y_3?,product_x2y3);
Multiplier_16x16??Multiplier_16x16_24(multiplier_x_2?,multiplier_y_4?,product_x2y4);
Multiplier_16x16??Multiplier_16x16_31(multiplier_x_3?,multiplier_y_1?,product_x3y1);
Multiplier_16x16??Multiplier_16x16_32(multiplier_x_3?,multiplier_y_2?,product_x3y2);
Multiplier_16x16??Multiplier_16x16_33(multiplier_x_3?,multiplier_y_3?,product_x3y3);
Multiplier_16x16??Multiplier_16x16_34(multiplier_x_3?,multiplier_y_4?,product_x3y4);
Multiplier_16x16??Multiplier_16x16_41(multiplier_x_4?,multiplier_y_1?,product_x4y1);
Multiplier_16x16??Multiplier_16x16_42(multiplier_x_4?,multiplier_y_2?,product_x4y2);
Multiplier_16x16??Multiplier_16x16_43(multiplier_x_4?,multiplier_y_3?,product_x4y3);
Multiplier_16x16??Multiplier_16x16_44(multiplier_x_4?,multiplier_y_4?,product_x4y4);
//左移即乘以2的n次方
always@(posedge?clk)begin
?product_x1y1_full<=product_x1y1<<96;
?product_x1y2_full<=product_x1y2<<80;
?product_x1y3_full<=product_x1y3<<64;
?product_x1y4_full<=product_x1y4<<48;
end

点击链接获取代码文件：http://www.hdlcode.com/index.php?m=home&c=View&a=index&aid=663