基于FPGA的64bits算术乘法器设计Verilog代码Quartus仿真

名称：基于FPGA的64bits算术乘法器设计Verilog代码Quartus仿真

软件：Quartus

语言：Verilog

代码功能：

设计64bits算术乘法器

基本功能:

1.用 Veriloghdl设计实现64bit二进制整数乘法器,底层乘法器使用16*168*88*328*16小位宽乘法器来实现,底层乘法器可以使用FPGA内部IP实现;

2.基于 modelsim仿真软件对电路进行功能验证;

3.基于 Quartus平台对代码进行综合及综合后仿真,芯片型号不限;

4.电路综合后的工作频率不低于50MHz。

提交 Veriloghdl设计代码,代码具有可综合性;

分别给出综合前后的仿真结果,并对比分析;

给出综合后电路的硬件资源及性能(如工作速度)等相关数据,简要分析资源和性能之间的关联性。

FPGA代码Verilog/VHDL代码资源下载：www.hdlcode.com

演示视频：

设计文档：

1. 工程文件

2. 程序文件

3. 程序编译

4. RTL图

5. Testbench

6. 仿真图

可以看到，乘积正确

综合后仿真

部分代码展示:

//?megafunction?wizard:?%LPM_MULT%VBB%
//?GENERATION:?STANDARD
//?VERSION:?WM1.0
//?MODULE:?lpm_mult?
//?============================================================
//?File?Name:?mul_16.v
//?Megafunction?Name(s):
//?lpm_mult
//
//?Simulation?Library?Files(s):
//?lpm
//?============================================================
//?************************************************************
//?THIS?IS?A?WIZARD-GENERATED?FILE.?DO?NOT?EDIT?THIS?FILE!
//
//?13.0.1?Build?232?06/12/2013?SP?1?SJ?Full?Version
//?************************************************************
//Copyright?(C)?1991-2013?Altera?Corporation
//Your?use?of?Altera?Corporation's?design?tools,?logic?functions?
//and?other?software?and?tools,?and?its?AMPP?partner?logic?
//functions,?and?any?output?files?from?any?of?the?foregoing?
//(including?device?programming?or?simulation?files),?and?any?
//associated?documentation?or?information?are?expressly?subject?
//to?the?terms?and?conditions?of?the?Altera?Program?License?
//Subscription?Agreement,?Altera?MegaCore?Function?License?
//Agreement,?or?other?applicable?license?agreement,?including,?
//without?limitation,?that?your?use?is?for?the?sole?purpose?of?
//programming?logic?devices?manufactured?by?Altera?and?sold?by?
//Altera?or?its?authorized?distributors.??Please?refer?to?the?
//applicable?agreement?for?further?details.
module?mul_16?(
dataa,
datab,
result);
input[15:0]??dataa;
input[15:0]??datab;
output[31:0]??result;
endmodule
//?============================================================
//?CNX?file?retrieval?info
//?============================================================
//?Retrieval?info:?PRIVATE:?AutoSizeResult?NUMERIC?"1"
//?Retrieval?info:?PRIVATE:?B_isConstant?NUMERIC?"0"
//?Retrieval?info:?PRIVATE:?ConstantB?NUMERIC?"0"
//?Retrieval?info:?PRIVATE:?INTENDED_DEVICE_FAMILY?STRING?"Cyclone?III"
//?Retrieval?info:?PRIVATE:?LPM_PIPELINE?NUMERIC?"0"
//?Retrieval?info:?PRIVATE:?Latency?NUMERIC?"0"
//?Retrieval?info:?PRIVATE:?SYNTH_WRAPPER_GEN_POSTFIX?STRING?"1"
//?Retrieval?info:?PRIVATE:?SignedMult?NUMERIC?"0"
//?Retrieval?info:?PRIVATE:?USE_MULT?NUMERIC?"1"
//?Retrieval?info:?PRIVATE:?ValidConstant?NUMERIC?"0"
//?Retrieval?info:?PRIVATE:?WidthA?NUMERIC?"16"
//?Retrieval?info:?PRIVATE:?WidthB?NUMERIC?"16"
//?Retrieval?info:?PRIVATE:?WidthP?NUMERIC?"32"
//?Retrieval?info:?PRIVATE:?aclr?NUMERIC?"0"
//?Retrieval?info:?PRIVATE:?clken?NUMERIC?"0"
//?Retrieval?info:?PRIVATE:?new_diagram?STRING?"1"
//?Retrieval?info:?PRIVATE:?optimize?NUMERIC?"0"
//?Retrieval?info:?LIBRARY:?lpm?lpm.lpm_components.all
//?Retrieval?info:?CONSTANT:?LPM_HINT?STRING?"MAXIMIZE_SPEED=5"
//?Retrieval?info:?CONSTANT:?LPM_REPRESENTATION?STRING?"UNSIGNED"
//?Retrieval?info:?CONSTANT:?LPM_TYPE?STRING?"LPM_MULT"
//?Retrieval?info:?CONSTANT:?LPM_WIDTHA?NUMERIC?"16"
//?Retrieval?info:?CONSTANT:?LPM_WIDTHB?NUMERIC?"16"
//?Retrieval?info:?CONSTANT:?LPM_WIDTHP?NUMERIC?"32"
//?Retrieval?info:?USED_PORT:?dataa?0?0?16?0?INPUT?NODEFVAL?"dataa[15..0]"
//?Retrieval?info:?USED_PORT:?datab?0?0?16?0?INPUT?NODEFVAL?"datab[15..0]"
//?Retrieval?info:?USED_PORT:?result?0?0?32?0?OUTPUT?NODEFVAL?"result[31..0]"
//?Retrieval?info:?CONNECT:?@dataa?0?0?16?0?dataa?0?0?16?0
//?Retrieval?info:?CONNECT:?@datab?0?0?16?0?datab?0?0?16?0
//?Retrieval?info:?CONNECT:?result?0?0?32?0?@result?0?0?32?0
//?Retrieval?info:?GEN_FILE:?TYPE_NORMAL?mul_16.v?TRUE
//?Retrieval?info:?GEN_FILE:?TYPE_NORMAL?mul_16.inc?FALSE
//?Retrieval?info:?GEN_FILE:?TYPE_NORMAL?mul_16.cmp?TRUE
//?Retrieval?info:?GEN_FILE:?TYPE_NORMAL?mul_16.bsf?FALSE
//?Retrieval?info:?GEN_FILE:?TYPE_NORMAL?mul_16_inst.v?TRUE
//?Retrieval?info:?GEN_FILE:?TYPE_NORMAL?mul_16_bb.v?TRUE
//?Retrieval?info:?GEN_FILE:?TYPE_NORMAL?mul_16_syn.v?TRUE
//?Retrieval?info:?LIB_FILE:?lpm

点击链接获取代码文件：http://www.hdlcode.com/index.php?m=home&c=View&a=index&aid=661