32位booth算法有符号乘法器设计VHDL代码modelsim仿真

名称：32位booth算法有符号乘法器设计VHDL代码modelsim仿真

软件：modelsim

语言：VHDL

代码功能：32位booth算法有符号乘法器

FPGA代码Verilog/VHDL代码资源下载：www.hdlcode.com

演示视频：

设计文档：

1. 程序文件

2. 程序编译

3. Testbench

4. 仿真图

Using Booth’s Algorithm for Signed

Multiplication

1.Booth’s Algorithm

2.Booth’s Algorithm (Procedure)

部分代码展示:

LIBRARY?ieee;
USE?ieee.std_logic_1164.all;
use?ieee.numeric_std.all;
USE?IEEE.STD_LOGIC_UNSIGNED.ALL;
entity?mult?is?
generic?(
?????NBITS?????????????????????:?integer?:=?32);
port(
????????prod??????????????????:?out?std_logic_vector(63?downto?0);
done??????????????????:?out?std_logic;
opa???????????????????:?in?std_logic_vector(31?downto?0);
opb???????????????????:?in?std_logic_vector(31?downto?0);
stb???????????????????:?in?std_logic;
rst_b?????????????????:?in?std_logic;
clk???????????????????:?in?std_logic);
end?mult;
architecture?behavior?of?mult?is
constant?NBITS_zero_1??:?std_logic_vector(NBITS?downto?0)?:=?(others?=>?'0');
constant?NBITS_zero??:?std_logic_vector(NBITS-1?downto?0)?:=?(others?=>?'0');
--?stb?machine
type?state_type?is(init,?load,?right_shift,?done_mul);
signal?state,?nxt_state?????????????:?state_type;
--control?signals
signal?shift????????????????????????:?std_logic;
signal?add_and_shift????????????????:?std_logic;
signal?add_and_shift_2??????????????:?std_logic;
signal?load_data????????????????????:?std_logic;
--?data?signals
signal?reg_A??????????????????:?std_logic_vector(2*NBITS?downto?0)?:=?(others?=>?'0');
signal?reg_S??????????????????:?std_logic_vector(2*NBITS?downto?0)?:=?(others?=>?'0');
signal?reg_P??????????????????:?std_logic_vector(2*NBITS?downto?0)?:=?(others?=>?'0');
signal?sum_A??????????????????:?std_logic_vector(2*NBITS?downto?0)?:=?(others?=>?'0');
signal?sum_S??????????????????:?std_logic_vector(2*NBITS?downto?0)?:=?(others?=>?'0');
signal?opa_complement?????:?std_logic_vector(NBITS-1?downto?0)?:=?(others?=>?'0');
constant?maxcount???????????????????:?integer?:=?NBITS-1;
signal?count????????????????????????:?integer?range?0?to?maxcount?:=?0;
signal?stb_mult_lead??????????????:?std_logic?:=?'0';
signal?stb_mult_follow????????????:?std_logic?:=?'0';
signal?stb_mult???????????????????:?std_logic?:=?'0';
begin
???--edge?detection?circuitry
???--?strat_count?=?'1'?on?the?rising?edge?of?the?stb?opa
???stb_mult?<=?stb_mult_lead?and?(not?stb_mult_follow);
???stb_mult_proc:?process(clk)
????????begin?
if(rising_edge(clk))then
????if(rst_b?=?'0')?then
????stb_mult_lead?<=?'0';
stb_mult_follow?<=?'0';
else?
????stb_mult_lead?<=?stb;
stb_mult_follow?<=?stb_mult_lead;
end?if;
end?if;
end?process?stb_mult_proc;
--2?process?atate?machine
state_proc:?process(clk)
????begin
if?rising_edge(clk)?then
???if(rst_b?=?'0')?then
??????state?<=?init;
???else
??????state?<=?nxt_state;
???end?if;
end?if;
end?process?state_proc;
state_machine:?process(state,?stb,?stb_mult,?count,?reg_P(1?downto?0))
???begin
???--?initialize?nxt_state?and?control?signals
???nxt_state?<=?state;
???shift?<=?'0';???????add_and_shift?<=?'0';?add_and_shift_2?<=?'0';
???load_data?<=?'0';???done?<='0';
???
???case?state?is
???????when?init?=>
??????if(stb_mult?=?'1')?then
??????nxt_state?<=?load;
??end?if;
???when?load?=>
??????load_data?<=?'1';
??nxt_state?<=?right_shift;
???when?right_shift?=>
??????if(count?=?maxcount)?then
??????nxt_state?<=?done_mul;
??end?if;
??if(reg_P(1?downto?0)?=?"01")?then
??????add_and_shift?<=?'1';
??elsif(reg_P(1?downto?0)?=?"10")?then?
??add_and_shift_2?<=?'1';
??else
??????shift?<=?'1';
??end?if;
???when?done_mul?=>
??????done?<=?'1';
??if(stb?=?'0')?then
?????nxt_state?<=?init;
??????end?if;
???when?others?=>
?????????nxt_state?<=?init;
???end?case;
end?process?state_machine;

点击链接获取代码文件：http://www.hdlcode.com/index.php?m=home&c=View&a=index&aid=1123