名称:波形发生器设计VHDL代码Quartus仿真
软件:Quartus
语言:VHDL
代码功能:
波形发生器
FPGA代码Verilog/VHDL代码资源下载:www.hdlcode.com
演示视频:
设计文档:
1.工程文件
2.程序文件
3.程序运行
4.RTL图
5.仿真文件
6.程序仿真图
4选一
波形产生模块
部分代码展示:
LIBRARY?ieee; ???USE?ieee.std_logic_1164.all; ???USE?ieee.std_logic_unsigned.all; --波形发生模块 ENTITY?carrier_wave?IS ???PORT?( ??????clk??????????????:?IN?STD_LOGIC; ??????rst??????????????:?IN?STD_LOGIC; ??????triangular_wave??:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0); ??????sawtooth_wave????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0); ??????square_wave??????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0); ??????sin_wave?????????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0) ???); END?carrier_wave; ARCHITECTURE?behaviour?OF?carrier_wave?IS ??? ???SIGNAL?sin_valu????????:?STD_LOGIC_VECTOR(7?DOWNTO?0)?:=?"00000000"; ???SIGNAL?count???????????:?STD_LOGIC_VECTOR(4?DOWNTO?0)?:=?"00000"; ??? ???SIGNAL?sawtooth_valu???:?STD_LOGIC_VECTOR(7?DOWNTO?0)?:=?"00000000"; ??? ???SIGNAL?square_valu?????:?STD_LOGIC_VECTOR(7?DOWNTO?0)?:=?"00000000"; ??? ???SIGNAL?triangular_valu?:?STD_LOGIC_VECTOR(7?DOWNTO?0)?:=?"00000000"; BEGIN ???PROCESS?(clk) ???BEGIN ??????IF?(clk'EVENT?AND?clk?=?'1')?THEN ?????????IF?(rst?=?'1')?THEN ????????????count?<=?"00000"; ?????????ELSIF?(count?=?"11111")?THEN ????????????count?<=?"00000"; ?????????ELSE ????????????count?<=?count?+?"00001"; ?????????END?IF; ??????END?IF; ???END?PROCESS;
点击链接获取代码文件:http://www.hdlcode.com/index.php?m=home&c=View&a=index&aid=1366
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