基于FPGA的波形发生器设计VHDL代码Quartus仿真

名称：基于FPGA的波形发生器设计VHDL代码Quartus仿真

软件：Quartus

语言：VHDL

代码功能：

波形发生器

(1)产生正弦波、方波、三角波；

(2)测量范围1Hz-100KHz；

(3)失真度小于5%；

(4)幅度为100mV-5V。

FPGA代码Verilog/VHDL代码资源下载：www.hdlcode.com

演示视频：

设计文档：

DDS原理

1. 工程文件

2. 程序文件

ROM IP核

3. 程序编译

4. RTL图

5. Testbench

6. 仿真图

整体仿真图

相位累加器模块

波形选择模块

正弦波ROM

三角波ROM

方波ROM

部分代码展示:

LIBRARY?ieee;
???USE?ieee.std_logic_1164.all;
USE?ieee.std_logic_unsigned.all;
--DDS频率等于clk*N/2^13,clk为输入时钟，N为频率控制字frequency；2^13是因为ROM里面存储了8192个点，相位累加器位宽为13位
ENTITY?DDS_top?IS
???PORT?(
??????clk_in??????:?IN?STD_LOGIC;--时钟
??????wave_select??:?IN?STD_LOGIC_VECTOR(1?DOWNTO?0);--01输出sin，10输出方波，11输出三角波
??????frequency????:?IN?STD_LOGIC_VECTOR(9?DOWNTO?0);--频率控制字，控制输出波形频率，值越大，频率越大
??????amplitude????:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);--幅值控制字，值越大，幅值越大
wave?????????:?OUT?STD_LOGIC_VECTOR(15?DOWNTO?0)--输出波形
???);
END?DDS_top;
ARCHITECTURE?behave?OF?DDS_top?IS
--例化模块
--波形选择模块
???COMPONENT?wave_sel?IS
??????PORT?(
?????????clk_in??????:?IN?STD_LOGIC;
?????????wave_select??:?IN?STD_LOGIC_VECTOR(1?DOWNTO?0);
?????????douta_fangbo?:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????douta_sanjiao?:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????douta_sin????:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????wave?????????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0)
??????);
???END?COMPONENT;
???
--相位累加器模块
???COMPONENT?Frequency_ctrl?IS
??????PORT?(
?????????clk_in??????:?IN?STD_LOGIC;
?????????frequency????:?IN?STD_LOGIC_VECTOR(9?DOWNTO?0);
?????????addra????????:?OUT?STD_LOGIC_VECTOR(12?DOWNTO?0)
??????);
???END?COMPONENT;
--ROM表
COMPONENT?sin_ROM?IS
PORT
(
address:?IN?STD_LOGIC_VECTOR?(12?DOWNTO?0);
clock:?IN?STD_LOGIC??:=?'1';
q:?OUT?STD_LOGIC_VECTOR?(7?DOWNTO?0)
);
END?COMPONENT;
--ROM表
COMPONENT?fangbo_ROM?IS
PORT
(
address:?IN?STD_LOGIC_VECTOR?(12?DOWNTO?0);
clock:?IN?STD_LOGIC??:=?'1';
q:?OUT?STD_LOGIC_VECTOR?(7?DOWNTO?0)
);
END?COMPONENT;
--ROM表
COMPONENT?sanjiao_ROM?IS
PORT
(
address:?IN?STD_LOGIC_VECTOR?(12?DOWNTO?0);
clock:?IN?STD_LOGIC??:=?'1';
q:?OUT?STD_LOGIC_VECTOR?(7?DOWNTO?0)
);
END?COMPONENT;
???
???SIGNAL?addra?????????:?STD_LOGIC_VECTOR(12?DOWNTO?0);
???SIGNAL?douta_fangbo??:?STD_LOGIC_VECTOR(7?DOWNTO?0);
???SIGNAL?douta_sanjiao?:?STD_LOGIC_VECTOR(7?DOWNTO?0);
???SIGNAL?douta_sin?????:?STD_LOGIC_VECTOR(7?DOWNTO?0);
???SIGNAL?wave_temp?????????:??STD_LOGIC_VECTOR(7?DOWNTO?0);--波形
BEGIN
???
???--方波ROM,存储波形数据
???i_fangbo_ROM?:?fangbo_ROM
??????PORT?MAP?(
?????????clock???=>?clk_in,
?????????address??=>?addra,
?????????q??=>?douta_fangbo
??????);
???
???
???--三角波ROM,存储波形数据
???i_sanjiao_ROM?:?sanjiao_ROM
??????PORT?MAP?(
?????????clock???=>?clk_in,
?????????address??=>?addra,
?????????q??=>?douta_sanjiao
??????);
???
???
???--sin波ROM,存储波形数据
???i_sin_ROM?:?sin_ROM
??????PORT?MAP?(
?????????clock???=>?clk_in,
?????????address??=>?addra,
?????????q??=>?douta_sin
??????);
???
???
???--相位累加器
???i_Frequency_ctrl?:?Frequency_ctrl
??????PORT?MAP?(
?????????clk_in????=>?clk_in,
?????????frequency??=>?frequency,--频率控制字
?????????addra??????=>?addra--输出地址
??????);
???
???
???--波形选择控制
???i_wave_sel?:?wave_sel
??????PORT?MAP?(
?????????clk_in????????=>?clk_in,
?????????wave_select????=>?wave_select,--01输出sin，10输出方波，11输出三角波
?????????douta_fangbo???=>?douta_fangbo,--方波
?????????douta_sanjiao??=>?douta_sanjiao,--三角
?????????douta_sin??????=>?douta_sin,--正弦
?????????wave???????????=>?wave_temp--输出波形?
??????);
???
wave<=wave_temp*amplitude;--波形乘以幅值
END?behave;

点击链接获取代码文件：http://www.hdlcode.com/index.php?m=home&c=View&a=index&aid=737