波形发生器设计VHDL代码Quartus 21EDA-CPLD开发板

名称：波形发生器设计VHDL代码Quartus? 21EDA-CPLD开发板

软件：Quartus

语言：VHDL

代码功能：

信号发生器设计

信号发生器由波形选择开关控制波形的输岀,分别能输出正弦波、方波和三角波三种波形,波形的周期为2秒(由40M有源晶振分频控制)。考虑程序的容量,每种波形在一个周期内均取16个取样点,每个样点数据是8位(数值酒范:00000000~11111111)要求将D/A变换前的8位二进制数据(以十进制方式)输出到数码管动态演示出来。

FPGA代码Verilog/VHDL代码资源下载：www.hdlcode.com

本代码已在21EDA-CPLD开发板验证，21EDA-CPLD开发板如下，其他开发板可以修改管脚适配：

演示视频：

设计文档：

1.工程文件

2.程序文件

3.程序运行

4.RTL图

5.管脚分配

6.仿真文件

7.程序仿真图

部分代码展示:

LIBRARY?ieee;
???USE?ieee.std_logic_1164.all;
???USE?ieee.std_logic_unsigned.all;
ENTITY?wave_generation?IS
???PORT?(
??????sys_clk?????????:?IN?STD_LOGIC;--输入时钟????
??????wave_select?????:?IN?STD_LOGIC_VECTOR(1?DOWNTO?0);--波形选择
??????SEL?????:?OUT?STD_LOGIC_VECTOR(3?DOWNTO?0);--数码管位选
??????SEG?????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0)--数码管段选
???);
END?wave_generation;
ARCHITECTURE?behaviour?OF?wave_generation?IS
--分频模块，分频到8Hz
COMPONENT?div_8Hz?IS
???PORT?(
??????clk_in??:?IN?STD_LOGIC;--50MHz输入
??????clk_8Hz??:?OUT?STD_LOGIC--8Hz输出
???);
END?COMPONENT;
???--波形发生模块
COMPONENT?carrier_wave?IS
??????PORT?(
?????????clk?????????????:?IN?STD_LOGIC;
?????????triangular_wave?:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????square_wave?????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????sin_wave????????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0)
??????);
???END?COMPONENT;
--3选1模块，00输出0;01-方波;10-三角波;11-正弦波，wave_select控制3选1
COMPONENT?MUX_31?IS
???PORT?(
?????????triangular_wave?:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????square_wave?????:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????sin_wave????????:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????wave_select?????:?IN?STD_LOGIC_VECTOR(1?DOWNTO?0);
?????????wave_data???????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0)--波形输出
???);
END?COMPONENT;
--显示模块
COMPONENT?display?IS
???PORT?(
??????clk????????????:?IN?STD_LOGIC;
??????wave_data??????:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);--波形
??????SEL?????:?OUT?STD_LOGIC_VECTOR(3?DOWNTO?0);--数码管位选
??????SEG?????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0)--数码管段选
???);
END?COMPONENT;
???SIGNAL?wave_data:?STD_LOGIC_VECTOR(7?DOWNTO?0);
???SIGNAL?triangular_wave???:?STD_LOGIC_VECTOR(7?DOWNTO?0);
???SIGNAL?square_wave?????:?STD_LOGIC_VECTOR(7?DOWNTO?0);
???SIGNAL?sin_wave????????:?STD_LOGIC_VECTOR(7?DOWNTO?0);
SIGNAL?clk_8Hz????????:?STD_LOGIC;
BEGIN
--分频模块，分频到8Hz
div_8Hz_U:div_8Hz
???PORT?MAP(
??????clk_in=>sys_clk,--50MHz输入
??????clk_8Hz=>clk_8Hz--8Hz输出
???);
???
???--波形产生模块
???carrier_wave_ge?:?carrier_wave
??????PORT?MAP?(
?????????clk??????????????=>?clk_8Hz,
?????????triangular_wave??=>?triangular_wave,
?????????square_wave??????=>?square_wave,
?????????sin_wave?????????=>?sin_wave
??????);

点击链接获取代码文件：http://www.hdlcode.com/index.php?m=home&c=View&a=index&aid=560